Saturday, March 30, 2019

Design A 1 Bit Serial Adder Computer Science Essay

Design A 1 Bit nonpar al onenessel publication common viper Computer Science EssayThe main civilise of this scheme is to design a 1- rubbish back-to-back common viper, simulate its functionality and obtain a layout on silicon, development the 0.35 process from AMS. The electric circuit designed shows a on the job(p) att terminateant adder quantifying at (100MHz of nsecs) with a delay of 0.56910nsec. The argona of the layout is 99.3016.35 m2 in this technology. The circuit performs an 8- dapple asset in 0.569108 nsesc. The circuit subprograms a standard 1- instant large adder and it has a feedback loop using a D- swop in gear up to transmit the involve silicon chip to the next excitant order. The final layout item of intersection has 3-input pads and 2- issue pads, with power and ground pads.The process known as accomp any(prenominal)ing improver of double star come is intumesce known in the computing and units subject of performing much(prenominal) acco mpanying double star adjunct ordinarily lie in a fundamental portion of more complex computation devices. In the past, such series adders for binary meter croak vote down employed vacuum cleaner tube circuitry for the more or less part and open accordingly been subject to the disadvantages that they ar relatively in large size, fragile in configuration and be subject to operating(a) failures. These factors raise serious questions of disposition of components and problems of maintenance. The demonstrate plan serves to obviate the fore divergence difficulties and in essence provides a consecutive adder structure cap adequate to(p) of performing serious addition of binary issues. It is accordingly an object of the posture invention to provide an improved serial adder for drill in computing maskings.An object of the present invention resides in the grooming of an improved serial adder for binary digital applications employing magnetized amplifiers as components th ereof. An another(prenominal) object of the present invention is the provision of the serial adder for binary numbers which adders loafer be made in relatively smaller sizes. A salvage further object of the present invention resides in the provision of a computation device comprising, in combination, a plurality of magnetic amplifiers and a plurality of gating devices so link with one another that the mathematical process known as a serial moment addition. The binary adder of the present invention includes provision for selective coupling the input train pulses to be added as well as conceptualise pulses produced by the device itself to the plurality of doorways, and the supplys be adapted by themselves to selectively pass foretell pulses required for the function or inhi playion of the plurality of magnetic amplifiers mentioned supra. In digital systems, digital preindication processing and control systems we coffin nail control it when we be able to count. Addition is the fundamental operation for all these systems.The fastness and accuracy ar mettlesomely crookd by the adders we be use for the circuit design. common vipers ar precise important components in the digital components because of their extensive use in digital trading operations such as multiplication, entailment and division. The deed of binary operations inside a circuit would be greatly advanced by improving the surgical procedure of the digital adders. The main aim of aim the dapple serial adder is toPerform one bit at a time, using the number one bit operation results to influence the processing of posterior bits. It reduces the amount of ironware required as it passes all the bits in the equal logical system. However this approach needs 1/nth part of hardware when compared to the n-bit parallel adders. As we are using 1-bit or else of n-bits its structure reduces the foretoken routing and performs at high speed as we are using 1bit scan for the temporary store and one encompassing adder rather than an n-bit adder. The drop-off in the price of the logic results in taking n time cycles to execute this serial hardware, whereas parallel hardware executes in one clock cycle. This bit structure deals with the bit stream hence this have been successfully utilize in many applications like digital systems, digital signal processing, control systems etc. It was extremely popular in 2-5u technology range. The performance of a digital circuit break off is gauged by analysing its power dissipation, layout field of record and its operating speed.The main aim of this project is to design a 1-bit serial adder. Through this project research we astonish the knowledge of working doings and performance of the 1-bit serial adder. Adders are the basic components for the designing of any digital circuit. Adders are very important components in the digital components because of their extensive use in digital operations such as multiplication, su btraction and division. The execution of binary operations inside a circuit would be greatly advanced by improving the performance of the digital adders. The main aim of designing the bit serial adder is to perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. Here in this case the one bit serial adder is designed by using a flip over and full adder. .This circuit has deuce defends full adder salute for the addition of cardinal bits that are entered serially and irregular stage is flip- mighty stage which temporarily stores the guide until the next stage is processed. The temporary storage of the leave in the flip-flop depends on the clock pulse. Its design principle shows how the devil inputs entered serially. These two inputs volition be added by the full adder on with the carry which was temporarily stored by the flip-flop and gives us the summarise outturn and carry produce. The normal 1-bit serial adder use s the XOR inlets from the available stub program library. But in this XOR penetration there is an OR supply which normally reduces the performance of the XOR ingressway. therefrom the circuit has been modified by designing the XOR approach by using the NAND gate.What we would like to do now is find the subdued way to use the sub tractor along with the serial adder circuit. By using this sub tractor we can subtract the get down bit tax from high value.This binary sub tractor has been added to one of the input which we are persuasion to subtract the value. In our serial adder circuit the sub tractor is link up to the one of the inputs Y which is usually a XOR gate. This results in the subtraction of Y value from higher bit set.BACKGROUND2.1 AdditionAddition is a process of adding bits. Binary addition means adding binary bits 0s and 1s and sum and carry generated in binary farm in any signal processing. instantly lets consider the 4-bit addition example,As shown above A and B bits added swelled brotherhood out by rippling the carry at apiece stage and C4 as final carry obtained.2.2 SubtractionSubtraction is a process of adding a constructive bit to the negative bit. Negative of a bit means 2s flattery of it. This is cryptograph only when adding 1 bit to LSB of its 1s compliment. 1s compliment is nothing exclusively reversing the logic of the bits. Now lets consider the 4-bit subtraction example,The above subtraction technique dedicate to the subtracting a smaller binary from a larger binary. If it changes it just followed by few more locomote as change sign bit (MSB) to zero, because change it to its 2s compliment as before process.Metal-Oxide-Silicon knowledge base-Effect junction transistors (Mosfets)NMOS TransistorHere is a diagram of nmos transistorThe source and drain are connected to the two blobs of n-type semi take upor material. Thegate is on top, separated (and electrically insulated) from the rest of the transistor by a t hin layer of silicon dioxide (same material as sand doesnt conduct at all). The source and drain are separated by p-type material. This forms two diodes pointed in opposite directions (when you have n-type next to p-type material, you get a diode), so no current can flow mingled with the source and drain. When a high voltage (higher than the voltage level of the source, which is defined as the lower voltage of the two end terminals) is applied to the gate, it puts a positive safekee gloamingg on the gate. This attracts a negative charge in the region underneath the gate (opposite charges attract), forming a channel of negative charge carriers or an n-channel between the source and drain, which allows current to flow. So the nMOS transistor conducts when the gate is raised to the high voltage level, which we consider to be the logic level for 1 (true).PMOS junction transistorThe pMOS transistor is the dual of the nMOS transistor. You can look at the same diagram, but swap every n and p, and every + and -. Now, when the voltage at the gate is lower than the source (the higher voltage of the two end terminals for a pMOS transistor), we end up with a negative charge on the gate, which induces a positive channel underneath the gate, which allows current to flow. So the pMOS transistor conducts when the gate voltage is low, which we consider to be the logic level for 0 (false).The full names of what is being described are enhancement path n-channel or p-channel metal-oxide semiconductor field effect transistors (MOSFET). Enhancement mode refers to the fact that we have to create the channel by applying voltage to the gate. (There are also depletion mode transistors that have a channel built in to start with.) Field effect refers to the fact that were using the electric field from the charge at the gate to control things. Metal-oxide semiconductor refers to the fact that were using an oxide to insulate the gate from the rest of the transistor. The two types of t ransistors are named for the channel nMOS has an n-channel pMOS has a p-channel.CmosThere are many ways to move over logic render (not to be busted with the gate of the transistor) out of transistors. What Im showing here is the dominant way that gates are done in digital electronics today, but there are many variations out there. This is called static CMOS logic. Static refers to the fact that there are not clocks involved. CMOS stands for complementary metal-oxide semiconductor. The complementary means we have twain nMOS and pMOS transistors.The intuition behind this design style is aboveboard. start-off, you dont want to have nMOS and pMOS transistors entangled up close to each other, because they need to be created on varied types of substrate. So the natural style is to have a bunch of nMOS transistors unitedly that pull the railroad siding one way for certain input values, and a bunch of pMOS transistors together that pull the production the other direction for the other input values. It turns out to work better to have the nMOS transistors pull down toward logic 0 and the pMOS transistors pull up toward logic 1. This is both for electrical reasons (nMOS conducts 0 better pMOS conducts 1 better) and also to make it easy to get inverting gates.The following diagram showing how to make an inverter (a NOT gate)Such that we veritable CMOS Technology by combination of Pull-up lucre of PMOS Transistors and Pull-down network of NMOS Transistors. each the CMOS gates are constructed using as shown below.CMOS Constructed by, PMOS transistors in Pull-up network stage and NMOS transistors in Pull-down network stage. railroad siding going 1-0The Pull-down NMOS transistors discharges the output capacitance.OUTPUT going 0-1The output capacitance is supercharged through Pull-up PMOS transistors.MOSFETs change states in CMOS TransistorCMOS logic is better logic than PMOS and NMOS implementations individually. Because PMOS transistors are great at transmit ting a logic 0 to1 voltage without signal loss, NMOS transistors are great at transmitting a logic 1 to 0 voltage.4.2 NAND GATEConstructed by, As shown below PMOS transistors in parallel and NMOS transistors in series.OUTPUT going 1-0 The series NMOS transistors discharges the output capacitance.OUTPUT going 0-1The output capacitance is charged through parallel PMOS transistors.Circuit diagram of NAND entryLogic type of NAND GateTruth table of NAND GateABOUTPUT0010111011104.3 NOR GATEConstructed by, As shown NMOS transistors in parallel and PMOS transistors in series.OUTPUT going 1-0The parallel NMOS transistors discharges the output capacitance.OUTPUT going 0-1The output capacitance is charged through series PMOS transistors.Circuit diagram of NOR GateLogic symbol of NOR GateTruth table of NOR GateXOR GATEXOR is also called scoop shovel OR gate or EOR gate. This is a digital logic gate, which is utilize to express the function of Exclusive Disjunction. Its behavior is similar t o or gate with exclusive condition. Usually it is a 2-1 input output IC respectively.An output naughty (1) will be resulted if one, and only one of its 2 inputs is HIGH (1). Result of output LOW (0) both the inputs should be same both low or high. We can say EX-OR gate as maven or another, but not both.XOR gate is used to develop a binary addition. It gives the sum for inclined input bits. As shown above xor of 2 bits A and B gives its sum.A xor B = A.B + A.BCircuit diagram of xor gateBASIC common viper UNITAddition of two binary numbers is the most basic arithmetic operation i.e. two bits. A combinatory circuit which can add only two bits is known as half(prenominal) adder. A full adder is one that adds more than two bits i.e. three bits. Full adder uses two adders in its implementation. In this study full adder is the basic addition employed in all adders.HALF common viper half is a basic adder circuit that can perform addition of two bits and gives the output of sum and car ry. Half adder circuit uses an Exclusive-OR and AND gates for sum and carry outputs. XOR gate gives the sum output and carry output is given by the AND gate. X and Y are inputs S is sum and C0 is carry.S = X.Y + X.Y = X YC = X.YIts schematic representation is as shown in the figure.The law table of half adder is as shown below.XYSUMC00000011010101101K-MAPPING of half adder circuit is given as shown below.Sum, S = X YCarry, C0 = X.YFULL-ADDERFull adder can be formed by combining two half-adder circuits followed by the OR gate. It can perform the addition of three bits along with the carry input given as output from the previous one. The difference between half adder and full adder is that half adder cannot count more than two bits and cannot add the carry input which will be possible in full adder circuit. In this circuit, sum output is given by the XOR gate and the carry output is given by the AND gate followed by the OR gate. The stop consonant diagram of full adder circuit is as shown below.FULLADDERSum S = X Y CI = (X Y) CICarry C0 = (X .Y) + (X Y).CIAs shown in the above figure X, Y and CI are the adder inputs.The integrity table of the above circuit is as shown below.XYCISUMC00000000110010100110110010101011100111111By using K-map pivot mang we will get SUM and CARRY as followsSum S,Carry c0,D FLIP FLOPD- Flip flop is used in many applications. RS flip flop is the fundamental building block for the D- flip flop. It has only one entropy input. That is connected to the input S of RS flip flop where as D is inversely connected to the R input.. D- Flip flop is also having second input for holding the data which is known as Enable, simply represented as EN. The enable input is AND-ed with the D- Flip flop. D- Flip flop holds the data according to the clock pulse.It is constructed by using AND gates and NOR gates as shown in the below figure. D and EN are the inputs and Q and Q are outputs. The block diagram of the D-flip flop is as shown below.D- Fl ip flop acts as temporary data storage in the 1- bit serial adder. Its storage capacity depends on the number of stages. The storage capacity of the D- flip flop in this serial adder is the fall number bits (0 and 1) of digital data it can retain.Its truth table is a shown below.DENQQN0 locomote edge0X0Rising edge011Falling edgeQprevX1Rising edge10.The wave forms are attached in the results.CHAPTER 2SERIAL ADDERThe process known as serial addition of binary numbers is well known in the digital and units candid of performing such serial binary addition ordinarily comprise a basic portion of more complex computation devices. In the past, such serial adders for binary numbers have employed vacuum tube circuitry for the most part and have accordingly been subject to the disadvantages that they are relatively in large size, fragile in configuration and are subject to operating failures. These factors raise serious questions of disposition of components and problems of maintenance. The present invention serves to obviate the forego difficulties and in essence provides a serial adder structure capable of performing full addition of binary numbers. It is accordingly an object of the present invention to provide an improved serial adder for use in digital systems.The main aim of designing the bit serial adder is to perform one bit at a time, using the first bit operation results to influence the processing of subsequent bits. Here in this case the one bit serial adder is designed by using a D-flip flop and full adder. .This circuit has two stages full adder stage for the addition of two bits that are entered serially and second stage is D-flip flop stage which temporarily stores the carry until the next stage is processed. The temporary storage of the carry in the D-flip flop depends on the clock pulse. Its design principle shows how the two inputs entered serially. These two inputs will be added by the full adder along with the carry which was temporarily stored by the flip-flop and gives us the sum output and carry output. This is a practical serial adder that is used to add astream of two bits addition. First it takes the Least Significant Bits (LSB) in addition. Its block diagram is as shown in the figure.As shown in the above figure the inputs Xi and Yi are serially entered into the full adder along with the temporary carry from the D-flip flop i.e. Ci and gives the carry output Ci+1 and sum output Si.Hence serial adder is simple and because of feedback looping bit delays are expected. It can be constructed with very low cost and it is the perfect adder at low speed operations.Si = Ci Yi XiCi + 1 = Yi . Ci + Xi . Ci + Xi . Yi = Ci . (Xi Yi) + Xi . YiThe above equations represent the Sum and Carry outputs using Boolean equations.The construction of 1-bit serial adder is as shown in the figure. As shown in the figure the inputs X and Y are serially entered through the full adder along with the carry input which was the feedback output of full adder. In this circuit, sum output is given by the XOR gate and the carry output is given by the AND gate followed by the OR gate. D- Flip flop used in this circuit acts as a temporary storage of carry.TRUTH instrument panelXYC00SCO0011001101101011100100110011011110111001This entire design process and simulation can be done by using the mentor graphics reading 2005 software.Chapter 3Nand gate design of serial adder4.4 NAND gate is infract THAN NOR.As PMOS in parallel and NMOS in series the resultant renewal delay at NAND gate is lesser than delay of NOR gate computer architecture.To make PMOS as fast as NMOS we need enlarge channel and P-regions, but that leads to large silicon layout, and more cost and power wastage. So At same speed NOR is always larger than NAND. So it makes NAND more cost-efficient than NOR. W/L ratio of NAND gate is smaller than NOR gate.If inputs for gates are more then, NAND will be very hurrying than NOR.So we use sop implementation rather than pos.XOR GATE USING NAND GATESIn PMOS holes flow very slowly when compared to the electrons in the NMOS technology. Hence NMOS is faster than PMOS transistor. In NOR gate PMOS transistors are connected in series and in NAND gate PMOS transistors are connected in parallel hence NAND gate is faster than the NOR gate. Now considering another case to make this one bit serial adder little bit faster compared to the normal one bit serial adder the XOR gate is constructed by using the NAND gates which full treatment faster than the normal XOR gate. The reason for constructing this XOR gate is that in the fondness library we are using to design the entire circuit XOR gate internally contains an OR gate which usually reduces the performance of XOR gate. Its circuit diagram is as follows.XYOUT000011101110Its truth table is as shown below.D- Flip Flop using nand gatesD Flip-Flop is the most popular Flip-Flop. As its output takes the value of data ( D ) input when the positive edge of clock pu lse. D turn around can be interpreted as a unmannered memory cell.D Flip-flops are basically used as swop registers. As a D Flip-flop can produce a output signal with a time period delay of given clock pulse for an input signal i.e., one bit shifted skillful to the input given signal. The principle of D flip-flop is it captures the signal at the moment the clock goes high, and subsequent changes of the data lines do not influence Q until the rise of next clock edge. thus it works as a edge triggering mode at clock signal rising.D Flip-flop is constructed using NAND gates as shown above, where D and CLOCK are the inputs and Q and QN are the out puts.XYC00SCO0011001101101011100100110011011110111001CHAPTER 3SUBSTRACTORUp to now we have seen how simple logic gates perform binary addition. It is only rational to assume that the same circuit can also perform the binary subtraction. If we look at the possibilities involved in subtracting one bit number from another, we can quickly see that three of the four possible combinations are easy and straight forward. The fourth one involves a bit more.0 0 = 01 0 = 11 1 = 00 1 = 1, with a borrow bit.That borrow bit is just like a borrow in decimal subtraction it subtracts from the next higher order of magnitude in the overall number. The truth table of this sub tractor circuit looks like as shown below.This is an interesting result. The difference, X-Y, is still an exclusive-OR function, just as the sum for addition. The borrow is still an AND function, but is XY instead of XY.Adder/Subtractor logic developed using NAND gate (lower from higher)Addition is adding positive two bits. Subtraction is nothing but an addition where we add one positive bit to another negative bit. That means the second bit will be the positive number with negative polarity. We can metamorphose positive binary to negative binary by its 2s compliment.2s compliment is nothing but adding 1 bit to the LSB side of 1s compliment.1s compliment is i n any binary canon if we swap bits by 1 bit with 0 bit and 0 bit with 1 bit. That is flip the binary code image.1s compliment can be generated using XOR logic. when we give one pin of XOR gate dedicated to positive as logic 1, and other pin connected to the input binary bit, then output of EXOR will be swapped by 1s with 0s and 0s with 1s. At the same time other advantage is if the dedicated input pin is given logic, then out put will be same as input binary code.Such that in that whole circuit by ever-changing selective pin as 0 logic it works as adder and by changing selective pin as 1 logic it works as subtractors 1s compliment input.Let we consider A + B it is a simple addition,ForA B = A + (- B) = A + (B 1s compliment + 1)= A + B 1s compliment + 1As shown above to find A B we give the full adder inputs as a to A, b to B 1s compliment and finally c in as positive logic 1. Thus adding 2 bits of A And B in this way we get A- B.Above developed subtractor circuit subtracts lower value bit from higher value bit so in 0-1 condition its not valid.ADDER TRUTH remand WHEN EN =0ENXYC00SCO000110001101010101011001SUBSTRACTOR TRUTH TABLE WHEN EN =1ENXYC00SCO1001001011XX110110111101IMPLEMENTATIONThe entire process of designing and layout of the 1-bit serial adder circuit is done by using the mentor graphics version 2005. The required logic gates and flip flop has been taken from the effect library. erstwhile taking all the required components from the core library wiring has been done again using the core library. oneness wiring has been done the sheet has been saved and done the schematic check. Once the schematic check has been done successfully then the view point has been created. Once view point has been done successfully the circuit has been crusade for simulation. After having done the simulation successfully the output waveforms has been checked. This output waveforms results the working of the entire circuit design. Once we got the outputs exactly what we are looking for we then go for layout design. This layout design is also done by using the core library which is known as silicon layout. After finishing the layout we will check the overflow of the IC which we will get at the end of the process.ConclusionIn the project of One Bit Serial Adder we obtained the knowledge about the functionality of adders and developed a fast adder using NAND gate Logic. We even obtain the knowledge about CMOS technology and functionality of IC Gates. As we developed using NAND gate logic implementation the architecture of IC will be much faster and efficient.From the obtained results of Serial adder waveforms and IC design by comparing the theoretical and practical values are verified each other. Such that I can cease the developed ICs are well functioning in any application era with a delay of 0.5921ns.Finally I concluded that a 1-bit Serial adder is developed in Conventional, NAND gate architecture and Adder/Subtractor architectures IC design an d layout of IC design obtained and verified without errors. Functional and galvanising Characteristics studied similar to CMOS technology as they developed.

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